1. Field of the Invention
The present invention relates to analog-to-digital converters, and in particular to analog-to-digital converters that employ a successive approximation technique.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows a schematic block diagram of a conventional successive approximation analog-to-digital converter (ADC). Such an ADC is described, for example, in "The Art of Electronics", second edition 1989, P. Horowitz and W. Hill, Cambridge University Press.
The ADC 1 of FIG. 1 comprises a digital storage register (referred to as a successive approximation register or SAR) 3, a digital-to-analog converter (DAC) 5 and associated reference voltage generating circuit 7, a comparator 9, a control circuit 11 and associated clock generating circuit 13, and a digital output circuit 15.
In use of the FIG. 1 ADC, an analog input voltage V.sub.IN to be converted into a corresponding digital output word is applied to one input of the comparator 9. A "start conversion" signal is applied to one input of the control circuit 11. In response to this pulse, the control circuit 11 stores in the SAR 3 a first digital "trial" value, the most significant bit of which is one and the remaining bits of which are zero. This trial value in the SAR 3 is then loaded into the DAC 5 which produces a corresponding analog trial voltage V.sub.TRIAL that is applied to the other input of the comparator 9. The value of the first trial word is selected so that the trial voltage V.sub.TRIAL is initially set to half the full-scale output voltage of the DAC 5.
If the result COMP of the comparison between V.sub.IN and V.sub.TRIAL is that V.sub.IN is greater than V.sub.TRIAL, the most significant bit of the SAR 3 is left at 1. Otherwise, that most significant bit is reset to 0.
Then, in the next conversion cycle of the ADC 1, the second most significant bit of the SAR 3 is set to 1, the other bits being unchanged. The resulting new digital trial value is applied to the DAC 5 which generates a different V.sub.TRIAL. In dependence upon the result of the comparison performed by the comparator 9 between the new V.sub.TRIAL and V.sub.IN, the level of the second most significant of the SAR 3 is determined in the same manner as in the first conversion cycle.
Operation of the ADC 1 continues in this way over successive cycles until the level of the least significant bit of the SAR 3 has been determined. At this point the control circuit 11 outputs an "end of conversion" signal and enables the output circuit 15 so that the content of the SAR 3 is output as a digital output word D.
Successive-approximation ADCs, such as that shown in FIG. 1, are relatively accurate and fast, requiring only n settling times of the DAC for n-bit precision. Typical conversion times are in the range from 1 to 50 .mu.s, and accuracies of between 8 and 12 bits are commonly available.
However, the conversion speed of the FIG. 1 ADC is limited by the requirement that the decision regarding the level of each bit of the SAR 3 must be correct to an accuracy of better than 1 least significant bit (LSB). This is a particular problem in successive approximation ADCs where fast or high resolution is required, since before a valid decision for each bit can be made the analog circuits must settle accurately, and the comparator must resolve a small signal after a large overdrive.